The present invention relates to semiconductor manufacturing, and, more particularly, to CMOS circuits having borderless self-aligned metal contacts and methods for forming such circuits.
Metal contacts to complementary metal oxide semiconductors (CMOS) circuits are formed after the completion of the front end of line (FEOL) process modules. The devices are typically encapsulated in one or more dielectric materials and the surface of the substrate is planarized. A single or a combination of lithographic operations are performed to expose contact vias aligned to the source, drain and gate regions of the device. One or more reactive ion etching (RIE) processes are performed to remove the dielectric materials from the lithographically patterned regions. Upon completion of the etch process, the contact vias are filled with a suitable metallization for forming an ohmic contact to the underlying device structure.
As the gate pitch of a CMOS circuit decreases, the size and pitch of metal contacts must scale accordingly. Consequently, the alignment tolerance for the metal contacts with respect to the gate electrodes becomes more critical. Gross misalignment of the metal contacts may result in gate-to-source and gate-to-drain shorts, rendering the underlying devices inoperable. As the gate pitch shrinks below 80 nm in modern semiconductor devices, the incorporation of the gate electrodes, sidewall spacers and the metal contacts themselves shrinks the overlay tolerance to a point where the formation of metal contacts becomes a bottleneck for continued technology scaling.